Pulse rate multipler



Oct. 27, 1959 M. A. MEYER ErAL 2,910,237

PULSE RATE MULTIPLIER BERNARD M. GORDON BYWVWW ATTORNEY v Oct. 27, 1959 M. A. MEYER ETAL PULsE: RATE: MUL'rIPLnaRv 2 Sheets-Sheet 2 Filed Dec. 5. 1952 COUNTER STAGE n FIG.2

GATE n PRODUCT sus 2 sTAGEs STAGE 4 STAGE 5 PRODUCT WITH BINARY NUMBER MULTIPLIER CARRY TO STAGE 2 GATE PULSE TO G-I CARRY To STAGE 3| I I I l l GATE PULSE TO G-Z CARRY To STAGE 4 I l I GATE PULSE TO G3 I CARRY TO STAGE 5 I l I GATE PULSE TO G4 CARRY TO STAGE 6 l GATE PULSE TO G-S OIOIIOOOO TIME-0 FIG. 3 a

PRODUCT OUTPUT OF BUFFER A TTORNE Y United States Patent Op" PULSE RATE MULTIPLIER Maurice A. Meyer, Natick, and Bernard M. Gordon,

Concord, Mass., assignors to Laboratory For Elec- 'onics, Inc., Boston, Mass., a corporation of Delaware l Application December '5, 1952, Serial No. 324,312

8 Claims. (Cl. 23S-164) The present invention relates in general to electrical computation systems and more specifically concerns a novel multiplier circuit capable of continuously and reliably forming products of predetermined signals at exceptionally high speed, if required, with a minimum of conventional, dependable electronic components.

Within the broad subject classification of digital computers there have been described numerous forms of electronic multiplying circuits for yielding a digital output representing the product of two or more digitally expressed input numbers. The manner in which the input signals are represented often governs the ultimate choice of a multiplier. In the serial type, the multiplier receives simultaneously only a single digit from each of the multiplier and multiplicand, while in the so-called parallel systems all digits of both multiplier and multiplicand are introduced to the multiplier simultaneously. 'In some digital computing machines, both serial and parallel number representations are employed, and multipliers arey available for operation under the control of such mixed signals. It is, however, characteristic of substantially all available digital multiplying systems, irrespective of whether serial or parallel notation is used, that both multiplier and multiplicand are necessarily eX- pressed as a denite number of digits, and that the product is correspondingly a number of a iixed quantity of digits, each represented electrically.

The problems involved in electrical computation are somewhat diierent if one of the input signals is a train of pulses, the number of pulses per unit time being representative of a iirst quantity; while the other input signal represents a binary number having a prescribed number of digits. To illustrate the need for computation under these circumstances, consider a continuous wave Doppler radar system where `the frequency deviation of the signal return continuously indicates the relative radial velocity between the radar installation and the reilecting target,

and Where it is necessary to multiply this velocity by a iixed or variable quantity available in digital form within the radar system. A pulse train representing frequency deviation may be generated by a suitable discriminator, such as the circuit disclosed in the co-pending application of Bernard M. Gordon, entitled Digital Discriminator, Serial No. 319,571, tiled November 8, 1952, now Patent No. 2,858,425, or similar circuit. In order to use already known techniques to rind the desired product, it would iirst be necessary to convert the pulse train into a digitally expressed binary number of a txed number of digits, and furnish vthis number together with the one already in digital form to the multiplier to form the product. Such procedure is obviously costly of equipment, and the conversion process may adversely affect overall accuracy.

The present invention contemplates and has as a primary object the provision of a multiplier capable of furnishing a continuous response representing the product of a.v number available in some digital system of notation and a quantity represented by the number of events per unit time of, an input signal such asa pulse train. Al-

oithese terminalsis either energizedata preselected;

c Ice 2,910,237'i though the sources of multiplier and multiplicand are not in themselves essential to the invention, the rst of these is preferably taken in parallel binary notation and the second from a discriminator as noted above, or, from any pulse or alternating signal source whose instantanen having a number of events per unit time representative of the product of the lirst and second quantities.

Generally speaking, the continuous coding, referred to above is achieved by energizing a series of cascaded binary counter stages by the input signal, and applying the output of each stage to a cor-responding number of gate circuits which are either open or closed in accordance With the polarities of the binary multiplier potentials. The desired product is derived as the electrical combination of gate circuit outputs, provided that, as disclosed herein, no two gate circuits are permitted to pass output signals simultaneously.

It is therefore another object of this invention to provide a multiplier which includes means for effectively coding a pulse train for interaction with a binary number expressed as a system of parallel potentials, all simultaneously available.

Another object of the present invention is to provide means for altering a pulse rate by a multiplier.

` A further object of this invention is to provide novel means for gating through the outputs of all stages of a cascade counter in accordance with the dictates of a binary multiplier.

A still further object of this invention is to provide novel means for timing the outputs of counter stages for actuation of multiplier gates whereby all output signal pulses are properly sequenced to preclude error or am- With reference now to the drawings and more particu-Y larly to Fig. lthereof, there is illustrated the combination and interconnection of circuit elements formi-ng a multiplier incorporating vthe principles of this invention. The multiplicand herein designated as X is applied at terminal 11 as a pulse train whose repetition rate instantaneously is related to the absolute value of a particular quantity. There is basically no limitation on the wave-` form of this so-called pulse train; itsimply must be capa-V ble of being counted cyclically. Thus, the input signal X may be in the form of a sequence of spaced, sharply delined potential spikes of some polarity, or it may simply comprise a sinusoidal or square wave of iixed or uctuating frequency.

In the speciiic aspect of the invention disclosed in Fig.

A- 1, lthe multiplier signal, bearing the notation Y, is applied in binary form to a parallel array of nine terminals Y1, Y2, Ya, YQ, each associated with a digit of consecutively decreasing signicance of a nine-digit binary number, Y1 corresponding to the'most signilicant digit. Each Patented occa?, 19579v potential or is grounded, depending on Whether the associated digit of the binary number multiplier is l or O respectively. The parallel activating potentials for the nine multiplier terminals are derived from sonic suitable binary source (not shown) and these potentials may be fixed to represent a scale factor, or may in themselves be variable as a function of time.

Returning now to a consideration of the application of the multiplicand X, it is seen that this signal is used to energize the input lof a cascaded binary counter 13, having a number of individual stages to correspond with the number of binary multiplier terminals, which in this instance is nine. Two distinct signals are derived from each counter stage; one of which is used as a carryto trigger the stage immediately following, while the other represents the binary count of that stage. These weighted counts, it will be observed, are marked appropriately as X/Z, X/4, X/SlZ. No carry is required from the output of the final stage.

The weighted output of each counter stage is directly applied to a corresponding one of nine coincidence type gate circuits identiiied on the drawing as G-l, G-2, G-.9, which gates are either open or closed, as determined by whether the correspondingly numbered binary multiplier terminal coupled to that gate is activated o r not.

Each gate circuit output is coupled through an individual buffer circuit B, the function of which is to preclude interaction of gate circuit outputs, and the outputs of all buffer stages are then combined in parallel at output terminal 15, which furnishes an output signal having a number of events per unit time representative of the product of X and Y.

Prior to proceeding with a more detailed analysis of multiplier operation, the nature of the circuitry capable of performing the functions outlined will be discussed. With reference now to Fig. 2, there is shown a schematic circuit diagram of each of the basic elements treated in the preceding block diagram. So that the treatment of circuits might be quite general, the nth stage of counter 13 and the nth gate circuit, i.e., gate G-n, have been drawn together with the associated butter and input and output terminals. For assistance in setting the circuits shown in Fig. 2 into the pattern of Fig. l, the counter, gate, and buffer stages have correspondingly been enclosed in blocks.

Specifically, the nth counter stage comprises a single flip-flop formed of triode electron tubes V1 and V2,

`wherein the plates are resistively connected to a positive potential source B-land the cathodes grounded. The

plates and grids of the triodes are cross-coupled by red sistance-capacitance networks 21 and 22, and the grids are additionally resistively connected to a negative potential source B-. The input signal is applied to the stage through a ditferentiator formed of capacitor 23 and resistor 24 and through diodes 2S and 26 to the plates of tubes V1 and V2, respectively.

As previously noted in connection with Fig. l, two independent outputs are taken from each counter stage. This is shown in Fig. 2, where the iirst output is taken from the plate of tube VI through a difterentiator formed of condenser 31 and resistor 32, and the second from the grid of tube V2. For the counter stage shown, the input signal occurrences may be represented by For each negative signal appearing across ditferentiator resistor 24, negative triggers will be Vapplied to both plates. If it is assumed that tube VI is initially conducting and V2 is initially cut off, then the negative trigger input will have the effect of reversing this state and will provide a positive going square Wave output at the plate of `tube VI. The next negative trigger appearing across resistor 24 will restore the initial state of conduction and non-.conduction in tubes V1 and V2, respectively, and

provide a negative going signal output from the grid of tube V2. This negative going signal is differentiated in the succeeding stage to provide a negative trigger or carry pulse therein. Both output signals may be represented by one half the input, or

Thus, for counter stage n, an output from one tube furnishes the gate circuit input, while the output from the; other tube furnishes the carry to the next consecutive counter stage. For the ip-flop shown, twoinput pulses from the preceding stage are required to complete a cycle of operation. In the specific arrangement disclosed in Figs. 1 and 2 the iirst of these two input pulses generates an output to the gate, with no carry output; while the second input signal generates a carry output to the next stage, with no significant gate input signal. Evidently then, gate signal inputs may be generated in any stage of the cascaded counter only within the intervals between carries; or otherwise stated, in each stage carries and gate input pulses are generated alternately. The full advantage of this interlaced signal timing scheme will be set forth later in the discussion of Fig. 3, and the specitic numerical example presented therewith.

Coincidence gate n comprises essentially a pair of similarly poled diodes 35 and 36, both anodes of which are coupled through common resistor 37 to a positive potential source. The cathode of diode 36 is energized by the binary input potential at terminal Y, and to facilitate explanation, switch 41 which may be used to connect terminal Yn to a positive potential or to ground is shown connected to this point. In effect, the switch 41 and its associated potentials represent the binary multiplier source. It will be understood that when this binary input line is activated, terminal Yu is connected to the positive switch point, otherwise it is grounded.

The operation of the gate circuit is briefly as follows: With either or both of the diode cathodes at a low potential, or ground, junction 42 will also remain at a comparatively low potential due to diode conduction. How? ever, if the cathodes of both diodes are simultaneously made positive, the potential at junction 42 will rise sharp-A ly to deliver an output signal. When, as shown in the drawing, terminal Yn is activated by the application of a positive potential thereto, positive pulses appearing across resistor 32 will also appear at junction 42. lf terminal Yn is grounded instead, then positive signals appearing across resistor 32 will be ineffective and will not be transferred through the gate.

The gate output at iunction 42 is directly coupled to the buffer or isolating stage which, in its simplest form, is a diode 45 poled for the transfer of positive pulses through a common load resistor 46 to the output terminal 1'5. Y

Reviewing the operation of the nth stage as shown in Fig. 2, it will be observed that if the binary line at terminal Yn is made positive, all pulses appearing across resistor 32 and representing the output subevents of the nth counter stage will be transferred in the same time sequence through the buffer to output terminal 15. If, on the other hand, terminal Yn is grounded, no output from terminal 15 is obtained from the nth stage. However, the nth counter stage continues to be effective in transferring carries through to the succeeding stages to continue the count.

At this point, reference is once again made to Fig. l for an `analysis of the operation of the overall multiplier system. Consider the multiplicand X as a number of occurrences, and assume that the number of occurrences is to be multiplied by another number Y, where Y is less than unity, and is expressed in binary rotation. By applying the multiplicand to the nine cascaded binary counter stages, weighted outputs of X/ 2, X/4, X/512 subevents are continuously obtained and applied tothe corresponding gates. The multiplier Y is also applied to these gates in binary form and where a gate is simultaneously actuated vby multiplierand multiplicand signals, it will pass through the buiers and to the output terminal 15, the corresponding weighted counter output. The combination of all gate outputs will furnish the product of multiplicand and multiplier at terminal 15, provided that no two subevents occur at the same time on the lines coupling the individual counterstages to the correspondingly numbered gates.

Analytically, the'sub-product Pn, equalto the number of subevents, delivered by the nth gate may be expressed as:

Where Y,n represents the digit of nth signiiicance in the binary number representative of the quantityY and determines the effect of the nth multiplier terminal. Yn is either one or zero and determines respectively whether the corresponding line is activated or not'. The iinal product P is simply the summation of all sub-products:

Since the number of input events X corresponds to a iirst quantity independent of n, it may be moved outside the summation sign as indicated. Then, by recognizing that the desired product is XY, and matching coefficients in the equations the following relation is obtained:

7L Y=Z 1 Thus each term represents the contribution of each digit in the binary number representation of the number Y, characteristic of a second quantity.

As an example of such multiplication, if the input X were to be multiplied by 0.653, the nearest binary multiplier would be 101001110 and only terminals Y1,'Y3, Y6, Yq', and Ys are activated while the remaining terminals are grounded. The activated lines would represent decimal contributions of 0.5-1-0.125-l-0.016+0.008|0.004, respectively. Therefore the number of output events at terminal 15 will be equal to 0.653X. As X represents a number of input events per unit time, the number of output subevents at terminal 15 during the same per unit time interval represents the desired product XY.

' The accuracy of the multiplier illustrated in Pig. 1 should be considered. If an-n stage counter is used together with n input lines and gates, the input number at terminals Y1 Yg may be represented to within an absolute value of i/zntl. If n is equal to 9, as shown in Fig. 1, then an accuracy of 0.1% may be achieved. Greater or lesser accuracy as required may be achieved byrespectively increasing or decreasing the number of` stages in the system.

At various points in the preceding discussion, it has been indicated that it is essential to operation of the system that no two-pulses occur simultaneously on the lines connecting the counter stages to the respective gates. Thisvis, of course, evident since the output product is represented as-the sum of a number of time sequenced pulses. In the conventional type of cascaded binary counter, carries Vfrom stage to stage arev generally lar'pa'fV gated by the same pulses that are read out of. a stage. In such arrangements, when a pulse appears on the output line of the nth stage, it must also appear on the lines of all previous stages. lFor a multiplier as in Fig. 1, a. counter of the conventional type would, therefore, result in error due to the merging of output pulses from the gate circuits.

In Fig. 2, it was shown that the carry signal was propagated from thegrid of triode V2 while the gate signal was taken from the plate of triode V1 and that consequently carry and gate signals alternated in the output of each stage.. The elect of this novel output pulse selection arrangement is graphically illustrated in Fig. 3. Thus, on the first line in Fig. 3, there are shown thirty-two consecutive multiplicand input pulse representations corresponding to an X of thirty-two input events. Assuming now that these are applied to input terminal 11 of Fig. 1, and based upon the previous discussion of Fig. 2, stage 1 of counter 13 will yield as one output, a sequence of 16 carries, and as a second output, a sequence of 16 alternately spaced signals for application to gate G-l. Thus there are 16 carry and 16 output pulses for gate operation which occur in mutually exclusive time intervals.

Counter stage 2 responds only `to each pair of carry pulses from stage l to yield in turn one carry to counter stage 3 and one significant pulse to gate G-2. In a similar manner stages 3, 4, 5 n, each respond to two -pulses from the next preceding stage to furnish one pulse to the respective gate and one carry pulse to the next stage. for the first five stages, the carry outputs and the outputs to the gates being shown on the same time scale. It may -now be observed that no output pulse shown falls in time coincidence with any other counter stage output pulse. On the other hand carry outputs are quite frequently coincident in time, but the carry pulses do not pass through the gates and buers to contribute to the linal system output. Although the principle -that no two out puts may occur simultaneously has been demonstrated for ve stages only, it is elective for any number of counter stages used in the multiplier.

To illustrate system operation by reference to a speciiic example, assume that the binary number representing Y is 010110000, only terminals Y2, Y4 and Y5 will be energized to open the associated gates G-Z, G-4 and G-5, to

couple output pulses to terminal 15. Utilizing the equation Y.. Y-Tfr Yinihisexamp'leis line, eleven output pulses, as shown in the lowermost line will be provided on terminal 15 in the sequence indicated. Note then that the input was the quantity thirty-two, represented by the thirty-two input pulses for a given time, the multiplier was 11/ 32 set up in binary form on the Y terminals, and the product output XY was eleven,

represented by eleven output pulses occurring within thel same time period and appearing at terminal 15.

' It will also be observed that this interlaced pulse timing relationship is wholly independent of the frequency of input multiplicand pulses. In other words, noparticular' In Fig. 3, the effect of this arrangement is shown` time` spacing patternis required of the` inputpulses-in order-to insureV that the summation provided atiterminal does not include two' pulsesV whichzhave-occurred simultaneously.

The novel technique just described" for obtaining an'V interlaced timing pattern is highly dependable and-eco nomical. However, if preferred, thetcarrypulse'between4 stages could be used to actuate the gates, provided,y however, that auxiliary delay deviceswere inserted between each-counter stage and gate circuit. That fis to'say, if a; more conventional type of counter were'employed, an

array of delay circuits could'be employed to generate the interlaced timing patternshownlin Fig. 3.

From a consideration of the.V system detailsfset forth above, it will now be apparent that the multiplier.. discussed -is ofgeneral application and that itimay lie-adaptedl to specific waveforms and input signals simply by.-V appropriately changing the'natureofcounter. orgates. TheA specific gating technique illustrated. in Fig. 2 is, ofcourse, not the only coincidence gate arrayI usable, butthe illustrated circuit has the advantage thaty light4 weight-.relia-V bility and compactness may be achieved using semi-conductor componentsl such as crystal diodes. types of binary counters are available and most of thesemay be adapted as shown in Fig. 2 to provide the necessary interlaced timing pattern without auxiliary. components.

Although an electron tube Hip-flop capable of operation at exceptionally high counting speeds has been described, there are available other types whichihave the advantage of less weight and'greater durability. Among these are magnetic type counters and variations which include combinations of magnetic elements and .transistor components. T he specific design chosen will,.of course,

depend upon the nature of the signals involvedy and the` ultimate cost aspects thereof.`

With the invention describedV as embodiedv in a par` ticular form, it will be apparent thatnumerous modif cationsV and departures may now be made by` those skilled' in this electrical computationand other arts. Conse quently, the invention herein is tofbe: construed aslimiteding output and carry pulses and having an input energized by carry pulses from the preceding stage and anioutput providing a lesser numberv of output pulses than the preceding stage in said counter, means for selecting said output and carry pulses from a stage at the same rate but at diterent times, gate circuits respectively coupled to the output of each of said counter stages, means forcontrolling the response of each gate circuit in accordance with a binary number signal representative of a second quantity, and butler means for combining the outputs of said gate circuits to provide an output pulse trainhaving arate characteristic of the product of saidrstand second quantities.

2. A multiplier comprising, n cascaded binary counter stages, where n is an integer, means for applying a pulsed signal having a rate characteristic of a firstV quantity to the input of the rst of saidA cascadedbinary counter stages, each of said counter stages delivering output: and carry pulses and having an inputenergized by carry pulses from the preceding stage and an output providing a lesser number of output pulses than the preceding stage, n gate circuits each associated with a corresponding counter stage and having rst and second inputs and'providing a single output when -said inputsare substantially simultaneously activated, means coupling. the'outputof each of said counter stages to--the rstA input of the respective gate circuit, means'for impressing a signalarepresenting abinary number on saidgate circuitusecondin- Numerous puts, whereby a gate circuit selectivelyfenergized-byr said? putv terminal all of'said output pulses coupled to gate. circuit outputs, all-of the latter pulses beingdelivered to.

said output'terminal duringy mutually exclusive times...

3. Apparatus as in claim-2 and including buffer,- means` for combining the outputs ofsaid n gate Vcircuits,-fvvhereby a signalrepresentation is provided-of the product.V ofxa quantity represented by said binary number signaland.-

a signal applied to said binary counter.

4. Apparatus as in claim 2 and including n buier circuits having a common outputrload circuit, the input of each butter circuit being coupled to the output of a respective gate circuit.

5. Computation apparatus comprising, `a counter having a plurality oficascaded ipflop binary counter stages,

means for energizing said `counter with a rst input signal wherein information is represented as a number of 'ccf currences in a predetermined'unit of' time, means in eachy flip-hop counter stage for propagating carry signals to the following stage, means inv each ip-op counter stage for providing-count signals related=proportionately to said number of occurrences and arranged as to preclude simultaneous occurrence of said count signals, each ofr equal to the number of occurrences in said first input signal during the corresponding timeunitzmultipliedf by said number represented by said second input signal.

6. A multiplier comprising, a,- multi-stage cascaded counter, means for applying aiirst signal to said counter having a number of impulses per unit time characteristic of a first quantity, each of said counter stages providing: smaller numbers of output pulses per unit time than the preceding stage, a plurality of gate circuits each corresponding to a digit of diiferent significance in a binary number and energized by said output pulses from a respective one ofsaidcounter stages-,meansfor applying. a gate conditioning signal to 't1-respective. gate.I circuit.. only when the binary digit of corresponding signiiicance in said binary number is a tirst of theV two,binary values, each-of said gate circuits being responsive4 to the sub.- stantially simultaneous-application ofsaid outputsignals,` and said gate conditioning, signal. to provideoutput impulses occurring during mutually. exclusivetime. inter.- vals, an output terminal, andmeans for couplingallsaidY output impulses to saidoutput terminal.. l

7. A multiplier` comprising, a. multi-stagey cascaded counter, means for applyingafirst signal to saidcounter having a numberof impulses per unit time characteristic of a tirst quantity, each counter` stage providing` outputand carry pulses-during mutually exclusive-time intervals, apluralityv ofA gate circuits each corresponding. top-a' digit of different significance -in a binarynumberv and energizedf by said output pulses fromarespective one of saidzconnter stages, means for applying a gate conditioning signal-.toa respective gate circuitonly when the-binary digit of corresponding signiicance in said-binary numberis .airst of the `two binary values, each of said` gate. circuits being responsive to the substantially simultaneous applica:` tion of said outputsignals and said gate conditioning signal to provide output impulses; means for applying said carry pulses to tlie input of'a followingl stage toof impulses per unit time representative of the product of said first quantity with said binary number.

8. Apparatus for providing an output signal having a number of impulses per unit time characteristic of the product of a rst quantity represented by the impulses per unit time of an input signal and a number represented by a plurality of digit signals each of which may assume first and second values corresponding to respective bit values indicative of said number in binary notation comprising, means responsive to said input signal impulses for providing gating impulses occurring during mutually exclusive time intervals, respective gating means associated with each of said digit signals and responding to predetermined ones of said gating impulses only when the respective digit signal is said first value by providing gated impulses spaced in time from all others of said gated impulses, an output terminal, and means for coupling all said gated impulses to said output terminal, said predetermined ones of said' gating impulses being characteristic of the signiticanceof the bit corresponding to the respec- 2,568,724 2,590,110 Lippel Mar. 25, 1952 2,634,052 Bloch Apr. 7, 1953 2,641,740 Levy June 9, 1953 2,672,283 Y Havens Mar. 16, 1954 2,674,727 Spielberg Apr. 6, 1954 2,685,407 Robinson Aug. 3, 1954 2,700,504 Thomas Jan. 25, 1,955 2,714,658 Greenfield Aug. 2, 1955 2,715,678 Barney Aug. 176, 1955 2,764,343

Earp et al Sept. 25, 1951 Diener Sept. 25, 1956 

